Professor at the Electrical and Computer Engineering Department, University of Wisconsin-Madison, Madison, USA.
Computer architecture, High performance processor and system implementations, Instruction level distributed processing, Co-designed Virtual Machines, Trace processors, Power efficient processors
Research Summary :
His research group is investigating future processors and systems that provide high performance, power efficiency and high reliability.
The Strata Project is centered around a re-definition of architectural layering through Co-Designed Virtual Machines (VMs). These VMs contain a layer of implementation dependent software that is developed concurrently the hardware. The VM software layer resides in a section of physical main memory that is hidden from all conventional software. There are several components to the Strata Project:
1) Architecting flexible dynamic profiling methods -- Dynamic optimization of Java applications is driving this work. These methods can be implemented as part of a high performance Java virtual machine.
2) Instruction level distributed processors (ILDP) -- These processors use simple accumulator-based instruction sets and highly distributed microarchitectures to deal effectively with increasing on-chip wire delays. ILDP microarchtitectures are part of co-designed VMs that translate existing binaries using conventional instruction sets.
3) Micro-operating systems -- This implementaton-dependent software automatically detects program phase changes and tunes hardware to optimize power efficiency and performance. These Micro OSes will be a key part of co-designed VMs.
4) Multi-threaded co-designed VMs -- The co-designed paradigm can be extended to dynamic translation and optimization in multiprocessor systems. Applications are concurrent optimization threads, including speculative multi-threading.
5) Concurrent checking and fault recovery algorithms -- These enable checking of distributed operations such as cache coherence. A co-designed VM can oversee the checking operation and implement recovery algorithms.
1999 Eckert-Mauchly Award "for fundamental contributions to high-performance microarchitecture, including saturating counters for branch prediction, reorder buffers for precise exceptions, decoupled access/execute architectures, and vector supercomputer organization, memory, and interconnects."
Statistical Simulation of Symmetric Multiprocessor Systems, S. Nussbaum, J. E. Smith, to appear, 35th Annual Simulation Symposium, April 2002.
Dynamic Microarchitecture Adaptation via Co-Designed Virtual Machines, A. Dhodapkar, J. E. Smith, to appear International Solid State Circuits Conference, Feb. 2002.
Modeling Superscalar Processors via Statistical Simulation, S. Nussbaum, J. E. Smith,PACT '01, International Conference on Parallel Architectures and
Compilation Techniques, Barcelona, Sept. 2001.
Rapid Profiling via Stratified Sampling, S. Sastry, R. Bodik, J. E. Smith, 28th Int. Symposium on Computer Architecture, pp. 278-289, June 2001.
Dynamic Verification of Cache Coherence Protocols, J. Cantin, M. Lipasti, J. E. Smith, Workshop on Memory Performance issues, Gothenburg, Sweden, June 30, 2001.
Saving and Restoring Implementation Contexts with co-Designed Virtual Machines, A. Dhodapkar, J. E. Smith, Workshop on Complexity Effective Design, Gothenburg, Sweden, June 30, 2001.